1. Field of the Invention
The present invention relates to a liquid crystal display device. More particularly, the present invention relates to a compensation circuit for a common voltage according to a gate voltage, which compensates the common voltage in accordance with variation in a gate high voltage, to obtain an optimal common voltage.
2. Discussion of the Related Art
With the recent progress of an information-dependent society, the field of displays to visually express electric information signals has rapidly developed. As a result, various flat display devices having superior characteristics such as lightness, thinness, and low power consumption have been developed to rapidly replace for cathode ray tubes (CRTs).
Examples of flat display devices include a liquid crystal display device (LCD), a plasma display panel device (PDP), a field emission display devices (FED), an electro luminescent display device (ELD) and the like. These flat display devices commonly include, as an essential constituent element thereof, a flat display panel to realize an image. The flat display panel has a structure in which two transparent insulating substrates are assembled to face each other under the condition that an inherent luminous or polarizing material layer is interposed between the substrates.
Among flat display devices, the liquid crystal display device displays an image through control of light transmittance of liquid crystals using an electric field. The liquid crystal display device has been highlighted as a next generation display device with high value-added advantages with respect to notebook computers and large-screen TVs because of low power consumption, slimness, and large screen size thereof. Such a liquid crystal display device includes a liquid crystal panel having liquid crystal cells, a backlight unit to irradiate light to the liquid crystal panel and a drive circuit to drive the backlight unit and liquid crystal cells.
Hereinafter, a related art liquid crystal display device will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram illustrating a configuration of a related art liquid crystal display device.
As illustrated in FIG. 1, the liquid crystal display device includes a liquid crystal panel 10 to display an image. The liquid crystal panel 10 includes a plurality of gate lines GL, a plurality of data lines DL, and thin film transistors T arranged in the form of a matrix at crossings of the gate lines GL and data lines DL. The liquid crystal display device also includes a gate driver 30 to sequentially supply gate signals to respective gate lines GL of the liquid crystal panel 10, a data driver 50 to supply a data signal to the data lines DL of the liquid crystal panel 10, a timing controller 20 to receive control signals from an external source along with the data signal, and to control the gate driver 30 and data driver 50 in accordance with the received signals, a gamma circuit 60 to supply a gamma voltage to the data driver 50, and a common voltage circuit 70 to supply a common voltage Vcom to a common electrode (not shown) of the liquid crystal panel 10.
In particular, when the liquid crystal panel 10 is of a twisted nematic (TN) mode type, the liquid crystal panel 10 has a structure in which a first substrate and a second substrate are assembled under the condition that a liquid crystal layer is interposed between the first substrate and the second substrate. In this case, an image is displayed through control of light transmittance of liquid crystals according to intensity of an electric field established due to a voltage difference between the two substrates. A grayscale voltage corresponding to an image signal is applied to one of the two substrates, and the common voltage Vcom is applied to the other substrate, to establish an electric field due to a voltage difference between the grayscale voltage and the common voltage, and, as such, light transmittance of the liquid crystals is controlled.
When the liquid crystal panel 10 is of an in-plane switching (IPS) mode type in which both the image signal and the common voltage Vcom are applied to one substrate, the liquid crystal panel 10 has the same driving principle as the TN mode type, except for the electrode structure.
Hereinafter, operation of the related art liquid crystal display device will be described.
First, when control signals from the outside are supplied to the timing controller 20, the timing controller 20 generates a gate control signal to drive the gate driver 30 and a data control signal to drive the data driver 50 in response to the control signals, and supplies the gate control signal and data control signal to the gate driver 30 and data driver 50, respectively. When the timing controller 20 receives a data signal from an external source, the timing controller 20 rearranges the data signal, and supplies the resultant signal to the data driver 50.
Upon receiving the gate control signal, the gate driver 30 sequentially supplies gate drive signals to the liquid crystal panel 10 through respective gate lines GL on a per horizontal line basis for one frame.
Upon receiving the data control signal, the data driver 50 converts the digital data signal into an analog image signal, and simultaneously supplies the analog image signal to all data lines DL of the liquid crystal panel 10 on a per horizontal line basis.
In addition, the common voltage circuit 70 generates the common voltage Vcom, and supplies the common voltage Vcom to the common electrode of the liquid crystal panel 10.
Thus, the liquid crystal panel 10 displays grayscales of an image according to a voltage difference between the image signal supplied from the data driver 50 and the common voltage Vcom. For this reason, image quality is greatly influenced by the value of the common voltage Vcom.
FIG. 2 is a block diagram illustrating a configuration of a related art common voltage circuit.
As illustrated in FIG. 2, the related art common voltage circuit 70 includes an n-bit register 71 to receive input data SDA and an external clock signal, an n-bit memory 73 to store the input data SDA, a controller to control the n-bit memory 73, and a decoder 77 to convert binary data input from the n-bit register 71 into a selection signal. The common voltage circuit 70 also includes a plurality of resistors R1 to Rm to divide first and second input voltages VH and VL, and a switching unit 78 to output one of different voltages having m levels, which are obtained in accordance with voltage division by the resistors R1 to Rm.
An operator supplies an image signal for testing to the liquid crystal panel, to display an image on the liquid crystal panel, and then inputs an appropriate temporary common voltage to the common voltage circuit 70, to inspect the displayed image. Through inspection, the operator finds an optimal common voltage FVcom to minimize flicker.
In accordance with another method, the common voltage output from the common voltage circuit 70 is fed back, and a difference between the fed-back common voltage and a voltage from a variable resistor is amplified using the variable resistor and, as such, an optimal common voltage is found.
Meanwhile, a circuit to increase a gate high voltage VGH in a low temperature environment is configured, using a thermistor, in order to compensate for degradation of gate in panel (GIP) characteristics in a low temperature environment.
FIG. 3 is a diagram illustrating a gate high voltage output circuit in the related art liquid crystal display device. FIG. 4 is a graph depicting a variation in gate high voltage according to a temperature variation measured by a thermistor in the related art liquid crystal display device.
As illustrated in FIG. 3, the related art liquid crystal display device uses a variable circuit in which a gate high voltage VGH output from the liquid crystal display device is set to be varied from a voltage VFB to a voltage VRUTC, using a thermistor TH, when a resistance is increased at a low temperature and, as such, a gate high voltage VGH is increased when the voltage VRUTC increases.
That is, the thermistor TH senses ambient temperature and, as such, the resistance of the thermistor TH is increased when ambient temperature is low. An output signal from the thermistor TH is applied to a power IC P-IC. The power IC P-IC utilizes a variable circuit in which the voltage VRUTC is output, in place of the voltage VFB, when the detect signal from the thermistor TH represents low temperature, and the gate high voltage VGH is increased when the voltage VRUTC increases.
For example, FIG. 4 explains an example in which 34V is output as a gate high voltage when ambient temperature is lower than 0° C., and the gate high voltage is gradually lowered in accordance with an increase in ambient temperature when ambient temperature ranges between 0° C. and 10° C., and, as such, 29V is output as the gate high voltage when ambient temperature is higher than 10° C.
However, variation of gate high voltage in the related art case encounters the following problems.
That is, when the gate high voltage is increased in a low temperature, using the thermistor, the optimal common voltage may be varied and, as such, the optimal common voltage at low temperature may differ from the common voltage set at normal temperature.
The difference between the optimal common voltage at low temperature and the common voltage set at normal temperature may cause frame rate control (ERC) noise.
In addition, in the case in which a gate high voltage is generated, using a pumping circuit, the gate high voltage may have a ripple component, in particular, in a liquid crystal display device model exhibiting high load of the liquid crystal panel thereof, as in a double rate driving system. As a result, the common voltage in the panel is lowered.